1. Field
Example embodiments relate to vertical-type semiconductor devices and methods of manufacturing the same. More particularly, example embodiments relate to semiconductor devices including cells that are connected vertically to one another and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices can be categorized generally as volatile memory devices, e.g., dynamic random access memory (DRAM) or static random access memory (SRAM), and non-volatile memory devices, e.g., flash memory devices. The degrees of integration, operating speeds and capacitances of the semiconductor memory devices have been greatly improved due to expanding application fields thereof.
From a circuit point of view, a flash memory device of the non-volatile memory devices may be classified as either a NAND-type flash memory device or a NOR-type flash memory device. In the NAND-type flash memory device, unit strings including N transistors connected in series to one another may be connected in parallel between a bit line and a ground line. In the NOR-type flash memory device, each cell transistor may be connected in parallel between the bit line and the ground line.
Contemporary flash memory device are required to store a large amount of data. Thus, a plurality of the cell transistors may be required to be formed in a unit chip. However, further integration of such devices is limited by the substrate dimensions.
Recently, in order to improve the degrees of integration of memory devices, a method of forming cell transistors included in each unit chip in a vertical direction relative to the substrate has been researched. In particular, in the NAND-type flash memory device, the cell transistors can be stacked in a vertical direction to form a cell string, to thereby improve the degree of integration of a memory device.
However, when the cell transistors included in the flash memory device are formed to be stacked vertically, uniformity between operating characteristics of each of the cell transistors positioned in the vertical direction and operating characteristics of each of the cell transistors formed on the substrate is difficult to achieve. In particular, when a channel region of the cell transistor is formed using polysilicon, cell distribution characteristics of the cell transistor including polysilicon may be poor and the operating speed thereof may be decreased due to the reduction of cell current, as compared with the cell transistor including a channel region formed in the semiconductor substrate. Further, the durability of a tunnel oxide layer included in the cell transistor including polysilicon may be lowered, to thereby reduce reliability of the NAND flash memory device.
Further, when an opening is formed, in order to form a channel pattern of a pillar shape, the opening may have a sidewall inclination angle with respect to the substrate. Since the width of an upper portion of the opening needs to be increased due to the sidewall inclination, the width of the opening may not be reduced to a critical dimension level, and thus it may be difficult to highly integrate the memory device.
For these and other reasons, it is difficult to manufacture a non-volatile memory device ID including the cell transistors stacked in the vertical direction, to have high performance and high integration, and with high reliability.